Holiday
DELTA台達216 T5T6R5R6
本課程將介紹邏輯電路的設計與實作理論,包含了二進位、布林代數、組合電路設計,儲存單元正反器、記憶體。並將介 紹同步序列邏輯電路與有限狀態器之設計以及暫存器轉移階層設計方法。
Course keywords: Logic Design, Combinational Logic, Sequential Logic, Boolean Algebra 一、課程說明(Course Description) This course introduces the basic theory of digital logic design and the implementation of logic circuit. In the beginning, binary number systems, simple boolean algebra, and switching functions are presented. The optimization method for combinational logic, which is the most important portion of the digital logic design, will be presented in detail in this section. Then, basic storage registers such as D-flip-flop, J-K-flip flop etc will be introduced in the section of the synchronous sequential logic, which will form a foundation for useful control technique - finite-state machine. After that combination logic and sequential circuits are combined to support number control in the digital system. The design for the registers and counters are taught in different types. Finally, the basic description of digital logic, Register Transfer Level, will be introduced, which will form the basic concept to develop the digital system through the hardware description language. 二、指定用書 (Text Books) William J. Dally and R. Curtis Harting, Digital Design - A Systems Approach, 2013, Cambridge University Press. 三、教學方式 (Teaching Method) Lectures 四、教學進度 (Syllabus) 1) Digital Abstraction 2) Boolean algebra 3) Combinational logic design 4) Combinational building blocks 5) Artithmetic Circuits 6) Sequential Logic 7) Data Path Sequential Logics 五、成績考核 (Evaluation) Quiz 40%, Midterm Exam 30%, Final Exam 30% 六、可連結之網頁位址 eeclass 課程系統
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Average Percentage 71.55
Std. Deviation 17.53
平均百分制 71.32
標準差 18.4
平均百分制 72.1
標準差 15.01
平均百分制 74.11
標準差 16.55
平均百分制 78.78
標準差 15.77
平均GPA 2.99
標準差 1.2
平均百分制 67.91
標準差 16.41
平均百分制 72.3
標準差 18.09
本課程每週150分鐘,其餘時間由教授彈性運用。必須第一次上課到現場(老師同意後)先以書面登記加簽
資工系大學部,電機系大學部,電資院學士班大學部優先,第3次選課起開放全校修習
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