EE 6250-0

Brief

This course is devoted to the fundamental knowledge of testing Very Large-Scale Integrated circuits (VLSI). The emphasis is on the investigation of various technically feasible test solutions combining both Design-for- Testability hardware and Computer-Aided Design algorithms for test-pattern generation to ensure the overall testability and quality of manufactured ICs. It begins with the topics of fault modeling and fault simulation, followed by the algorithms of Automatic Test Pattern Generation (ATPG). Then, widely adopted Design-for-Testability (DFT) techniques in IC design industry, such as Scan Test, Built-In Self-Test (BIST), and test compression will be introduced. Upon the completion of this course, the students will know how to apply all kinds of test solutions to make an IC easily testable and reliable in a cost-effective way.

Description

Course keywords: VLSI, Design for Testability, Testing, Test Pattern Generation, Built-In Self-Test, Fault Diagnosis, Board-Level Testing 一、課程說明(Course Description) This course is devoted to the fundamental knowledge of testing Very Large-Scale Integrated circuits (VLSI). The emphasis is on the investigation of various technically feasible test solutions combining both Design-for- Testability hardware and Computer-Aided Design algorithms for test-pattern generation to ensure the overall testability and quality of manufactured ICs. It begins with the topics of fault modeling and fault simulation, followed by the algorithms of Automatic Test Pattern Generation (ATPG). Then, widely adopted Design-for-Testability (DFT) techniques in IC design industry, such as Scan Test, Built-In Self-Test (BIST), and test compression will be introduced. Upon the completion of this course, the students will know how to apply all kinds of test solutions to make an IC easily testable and reliable in a cost-effective way. 二、指定用書(Text Books) L.-T. Wang, C.-W. Wu, and X. Wen, “VLSI Test Principles and Architectures: Design for Testability,” Morgan Kaufmann, July 2006. 四、教學方式(Teaching Method) lecture with slides 五、教學進度(Syllabus) 1. Introduction 2. Fault Modeling 3. Fault Simulation 4. Design-for-Testability (DFT) and Scan Test 5. Automatic Test Pattern Generation (ATPG) 6. Delay Test 7. Built-In Self-Test (BIST) 8. Test Compression 9. Boundary Scan Test 10. Power and Clock Network Testing 11. Fault Diagnosis 六、成績考核(Evaluation) 出席5% 實作型作業30% 期中考30% 期末考35% 七、使用AI原則: 若作業使用到生成式AI的輔助，請於報告中註明生成式AI 的使用方式。 八、可連結之網頁位址 EECLASS https://eeclass.nthu.edu.tw/

Timetable

Scores

Average Percentage 88.42

Std. Deviation 9.77

Remarks

同步遠距課程

Restrictions

Compulsory

Elective

Cross Discipline

First Specialization

Second Specialization