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Holiday
EECS資電 105 M2W5W6
This course introduces the design and analysis of the phase-locked loop (PLL). It covers the phase domain analysis and modeling of the loop, building blocks, phase noise evaluation of the PLL. It also includes the applications of the PLL, especially the clock and data recovery (CDR) design for the wireline receiver.
MON | TUE | WED | THU | FRI | |
08:00108:50 | |||||
09:00209:50 | |||||
10:10311:00 | |||||
11:10412:00 | |||||
12:10n13:00 | |||||
13:20514:10 | |||||
14:20615:10 | |||||
15:30716:20 | |||||
16:30817:20 | |||||
17:30918:20 | |||||
18:30a19:20 | |||||
19:30b20:20 | |||||
20:30c21:20 |
Average Percentage 81.27
Std. Deviation 14.56
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