EE 3230-0

Brief

In this course, students will learn the basics knowledge of IC designs, focus on transitor-level circuits and chip-level designs methdology. You will also get familiar with the transitor-level IC- related CAD tools (design, simulation, layout, RC-extraction) after finishing all the assigned homeworks and project. This course targes at both "知識學習"與"動手做".

Description

Course keywords: IC designs, VLSI designs, Circuit designs, Chip designs, Semiconductor *課程說明(Course Description) In this course, students will learn the basics knowledge of IC designs, focus on transitor-level circuits and chip-level designs methdology. You will also get familiar with the transitor-level IC-related CAD tools (design, simulation, layout, RC-extraction) after finishing all the assigned homeworks and project. This course targes at both "知識學習"與"動手做". *教學方式(Teaching Method) 1. Lectures with power-point files 2. embedded Labs (Tutorial + TA hours) (at EE Workstation Room, strating from 2nd or 3rd week) 3. Videos of top IC-design conferences *教學進度(Syllabus) 1. Introductions 2. CMOS Devices and IC Process 3. Static and Dynamic CMOS Gates (Combination Logics) 4. Sequential CMOS Circuits 5. Interconnects and Parasitic effects 6. Memory and Array Structures 7. Chip Design Methodologies 8. Chip-level Optimizations 9. Trends and Challenges in Nano-scale IC * IC Design CAD Tools 1. HSPICE 2. Schematic Entry (Cadence-Composer) 3. Layout (Laker or Virtuoso) 4. DRC/LVS (Calibre) 5. RC extraction (Calibre) *成績考核(Evaluation: 50% exam, 50% practice) 2 Midterm exams: 35% (1st: 20%, 2nd: 15%) 1 Final Exam.: 15% 5 Homeworks (Labs): 30% (6% each) 1 Design Project (2 students per team): 20% 先修課程 (Suggested Course prerequisites): 1. Electronics (電子學) 2. Logic Designs (邏輯設計) 3. Circuit Theory (電路學) Text Book 1.“Digital Integrated Circuits: A Design Perspective” by Rabaey 2. IEEE Papers (ISSCC and IEEE JSSC) Important Note: 1. Lecture/Lab classes might end later than regular class schedule. 2. Labs and tutorials ("how to use CAD tools) will be embedded in regular course hours. 3. Additional TA hours in the evening will be available at EE workstation room 4. Limited number of seats are available. If you may not commit spending effort to finish project and homework, please vacant the seats to other students who are willing to commit.

Prerequisites

Timetable

Scores

Average Percentage 86.82

Std. Deviation 7.72

PTT Reviews

Remarks

本學期增開課程，非常態開設。

Restrictions

電機系大學部3年級4年級,電資院學士班大學部3年級4年級優先，第3次選課起開放全校修習

Compulsory

Elective

Cross Discipline

First Specialization

Second Specialization