CSR 5410-0

Brief

CMP is one of the most technology in the relentless progress of the CMOS devices towards smaller, faster and less expensive fabrication. However, there are still many challenges in the novel application and fundamental understanding of the CMP process with the associated defect and contamination issues. In this course, three directions are expected to: 1) To equip with sufficient CMP fundamental knowledge 2) To construct a comprehensive thinking model 3) To build up the ability in analyzing issues & proposing solutions

Description

Course keywords: 平坦化 (Planarization), 研磨墊(Polishing Pad), 研磨液(Slurry), 研磨碟(Disk), 凹陷(Dishing), 侵蝕(Erosion), 研磨速率(Polishing Rate), 均勻度(Uniformity), 選擇比(Selectivity) 一、課程說明： CMP has been widely applied for topography planarization and device structure formation. A flat surface can improve DOF limitation of lithography and poor step coverage of PVD deposition created by device 3D structure. In addition to, 3D integration of advanced packaging technologies is becoming the decisive factor beyond Moore's Law. CMP plays a vital role for the thinning process of 3D integration. It eliminates grinding marks and residual stress after thinning substrate materials. In this course, both experimental and theoretical contributions of CMP technology are included. Four major topics: Overview of CMP, hardware configuration, fundamental principle & process mechanism, CMP Technology Development & Challenge. 二、教學方式: Classes will be taught with PowerPoint presentations, and the course materials and supplementary teaching materials will be uploaded after the class 三、成績考核: 1. Attendence: 10% 2. Class Participation: 10% 3. Mid.Exam. (9th week): 40% 4. Final Exam. (18th week): 40% 四、課程內容大綱： Four topics to introduce CMP technology & application in CMOS device: 1) CMP Introduction (2 weeks): Overview the development history of planarization technology & CMP process application in CMOS device. 2) CMP Hardware Configuration(4 weeks): Highlight in key component of CMP hardware system included in carrier head, conditioning disk, polishing pad, slurry & cleaner. 3) CMP Fundamental Principe & Process Mechanism(7 weeks): Highlight in dielectric (oxide, low K, etc.) & metal (Al, W, Cu, etc.) materials polishing included in CMP theoretic modeling, fluid flow, particle adhesion, post-polish cleaning, metrology, performance index and their related issues 4) CMP Technology Development & Challenge(3 weeks): Highlight in recently CMP technology development & challenge especially in FinFET/Nanosheet/GAA device structure. 五、擬用教科書，參考書或教材來源： 教科書： S.V. Babu, S. Danyluk, M. Krishnan, M. Tsujimura, Chemical Mechanical Polishing – Fundamentals and Challenge, Cambridge University Press, 1st edition, 2000 參考書或教材：1. 蕭宏,半導體製程技術導論,全華圖書, (第三版), 2014 2. IEDM/VLSI/ICPT conference proceedings (supplementary materials) 六、採用下列何項 AI 使用規則 (Indicate which of the following options you use to manage student use of the AI): 本課程無涉及AI使用 Not applicable

Timetable

Scores

Average Percentage 86.12

Std. Deviation 4.68

Remarks

製程部選修

Restrictions

Compulsory

Elective

Cross Discipline

First Specialization

Second Specialization