Holiday
DELTA台達215 T5T6R6
The course is designed to provide the fundamental theories & techniques of digital VLSI design in CMOS technology and carry out a digital VLSI deign. In this course, we will study the fundamental knowledge of designing digital VLSI systems include the operating mode of a MOSFET transistor and basics of MOSFET modeling, the description of CMOS fabrication and design rules, the analysis of static and dynamic behaviors of CMOS logic gates, the design of combinational logic and the system-level circuits, the optimization concepts of circuit and layout designs. Laboratory and project works will be utilized on industrial standard tools.
● 課程說明(Course Description) The course is designed to provide the fundamental theories & techniques of digital VLSI design in CMOS technology and carry out a digital VLSI deign. In this course, we will study the fundamental knowledge of designing digital VLSI systems include the operating mode of a MOSFET transistor and basics of MOSFET modeling, the description of CMOS fabrication and design rules, the analysis of static and dynamic behaviors of CMOS logic gates, the design of combinational logic and the system-level circuits, the optimization concepts of circuit and layout designs. Laboratory and project works will be utilized on industrial standard tools. ● 指定用書(Text Books) CMOS VLSI Design, a circuits and system perspective, Heil Weste and David Harris, published by Pearson, 4th edition, March 2010. ● 參考書籍(References) 後補 ● 教學方式(Teaching Method) Lectures offered in English ● 教學進度(Syllabus) 1. Introduction 2. MOS Transistor Theory 3. CMOS Fabrication, Layout and Modelling 4. CMOS Inverter 5. Delay and Transient Response 6. Power and Interconnect 7. Design Margin and Reliability 8. Combinational Circuit Design 9. Sequential Circuit Design 10. Datapath Subsystems Lab: 1. Cadence Setup and Schematic Entry 2. Schematic Entry and Circuit Simulation 3. Hierarchical Schematic Design 4. Layout Editor and Design Rule Check 5. Layout Versus Schematic 6. Post-Layout Simulation Final Project: Logic circuit design (Simulation and optimization) ● 成績考核(Evaluation) (必填) Homework & Lab. Assignments: 30% Final project: 20% Midterm: 25% Final: 25% ● 採用下列何項 AI 使用規則 (Indicate which of the following options you use to manage student use of the AI) 禁止使用,請註明相關的監管機制 Prohibited use; please specify relevant oversight
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Average Percentage 76.16
Std. Deviation 12.12
平均百分制 86.82
標準差 7.72
平均百分制 83.19
標準差 12.22
16週,9/7~9加簽申請,9/10亂數決定加簽人數及順序(EE,EECS優先),開學後退選名額9/21第2次抽簽
電機系大學部3年級4年級,電資院學士班大學部3年級4年級優先,第3次選課起開放全校修習
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